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Simulating FET in Semiconductor Module

Posted 25.09.2016, 13:48 GMT-4 2 Replies

Sagnik Middya
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Hi,
I am trying to simulate a FET device in 3D (not Silicon) in the Semiconductor module. 2D model is working fine. But when i try to vary the W/L ratio, the solution does not converge. Is there any way to improve the convergence?
2 Replies Last Post 27.09.2016, 12:24 GMT-4
Daniel Connelly
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Posted: 8 years ago 26.09.2016, 16:21 GMT-4
Keys to convergence on semiconductor device simulations are mesh and discretization. In the latter, Scharfetter-Gummel is designed specifically for the nonlinearity of semiconductor equations. For the former, you want mesh to be sufficiently well resolved normal to the oxide/semiconductor interfaces, most specifically the gate insulator, and ramp all biases of direct contacts, don't just drop a volt on the drain for example (you can generally change the gate bias if it's fully insulated, though).


I'm guessing if W affects the convergence your mesh isn't good enough.
Keys to convergence on semiconductor device simulations are mesh and discretization. In the latter, Scharfetter-Gummel is designed specifically for the nonlinearity of semiconductor equations. For the former, you want mesh to be sufficiently well resolved normal to the oxide/semiconductor interfaces, most specifically the gate insulator, and ramp all biases of direct contacts, don't just drop a volt on the drain for example (you can generally change the gate bias if it's fully insulated, though). I'm guessing if W affects the convergence your mesh isn't good enough.
Daniel Connelly
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Posted: 8 years ago 27.09.2016, 12:24 GMT-4
Also if you're using a wide-gap semiconductor, note this yields more challenging convergence, especially at higher drain bias, since you simultaneously have a large number of one carrier type and a very small number of the opposite carrier type. If you swap out a wide-gap semiconductor for silicon you can check if it's the semiconductor contributing to the problem.
Also if you're using a wide-gap semiconductor, note this yields more challenging convergence, especially at higher drain bias, since you simultaneously have a large number of one carrier type and a very small number of the opposite carrier type. If you swap out a wide-gap semiconductor for silicon you can check if it's the semiconductor contributing to the problem.

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